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From: dillon@flea.best.net (Matt Dillon)
Newsgroups: comp.unix.bsd.freebsd.misc
Subject: Re: freeBSD and P6/180
Date: 8 Nov 1996 00:54:42 GMT
Organization: BEST Internet Communications, Inc.
Lines: 96
Message-ID: <55u0ci$fl5@nntp1.best.com>
References: <32784DB5.2BDE@sybase.com> <3280D2FC.28D5@www.play-hookey.com> <57g22mmc2l.fsf@tees.elsevier.co.uk> <32823416.24F5@www.play-hookey.com>
NNTP-Posting-Host: flea.best.net
:In article <32823416.24F5@www.play-hookey.com>,
:Ken Bigelow <kbigelow@www.play-hookey.com> wrote:
:>Paul Richards wrote:
:>>
:>> Ken Bigelow <kbigelow@www.play-hookey.com> writes:
:>>
:>> > > You don't want a cpu at that speed either, make sure it's a multiple
:>> > > of 33 1/3 (roughly).
:>> >
:>> > Now you've got me puzzled. What's wrong with a multiple of 40 or 50 MHz
:>> > (always assuming the motherboard can run at one or the other of thoses
:>> > speeds)? I would expect that a higher motherboard speed would be
:>> > desirable, too.
:>> >
:>> > Could it be that the motherboard is expected to clock at 60 MHz for the
:>> > PP180? That would make more sense to me than running a 30 MHz clock and
:>> > a 6X multiplier.
:>>
:>> Yes. But it sounds like you've got an out of date notion of bus
:>> speeds. 40 and 50 Mhz is *slow*, you want to run the bus at
:>> 66Mhz. Running the bus at 60Mhz is a 6Mhz drop which people don't
:>> think is significant until you point out it's 10%
:>
:>Obviously I'm more limited by my pocketbook than I had realized. My site
:>is still running on an ISA/VLB motherboard (486DX50) with EIDE drive,
:>etc. I can upgrade to a 5x86-133 (AMD) which overclocks to 160, but with
:>a 33.6K dialup connection, this is the bottleneck in any case. Ah, well,
:>when I win the lottery.....
:>
:>Thanks for waking me up, although it'll still be awhile.
:>--
:>Ken
:>
:>Are you interested in |
:>byte-sized education | http://www.play-hookey.com
:>over the Internet? |
The real significance is as much in bus WIDTH as it is in bus
SPEED. The PCI bus only runs at 33 MHz (I think), but at 32 bits wide
you get as much as 130 MBytes/sec out of it when doing
burst DMA or burst pipelined writes. Compare that to ISA,
where you would be lucky to get 5 MBytes/sec out of it.
The dynamic rams used for memory are still the same old 70ns
SIMMs they have always been.. in fact, EDO is not fundamentally
different beyond the 'extended data out' portion... it's still
the same basic speed, just tuned such that a modern memory
controller can access it one clock faster.
The difference is that on a pentium class machine two SIMMs
are accessed in parallel.. 64 bits rather then 32, doubling
the effective throughput. If you add interleaving (with
four SIMMs), you double it again.
CPU caches are now a whole lot larger and a whole lot wider..
A typical instruction cache is 128 to 256 bits wide.
Something like the pentium (pro) gets 200 MIPS (200 MILLION
instructions per second) by accessing a slower, but very
much wider cache subsystem. RISC chips generally work the
same way. Instruction execution is effectively decoupled
from the memory and, except for reads, the I/O subsystem,
allowing instructions to be executed at 10 times the rate
the nominal memory subsystem would otherwise be able to support.
On the other hand, most RISC processors, including the
pentium come back down to earth with certain types of
non-cacheable or badly-cachable accesses. For example,
a read-modify-write in a video frame buffer is usually
non-cacheable and may be eight times slower then a simple
write to the same video frame buffer (which can be pipelined
and not have to stall the instruction stream). Many RISC
processors go to great lengths to avoid these bottlenecks.
For example, the pentium employs a branch-prediction cache
in an attempt to keep the instruction pipeline full even
through branches, calls, and jumps. A single cache miss is
roughly equivalent to 20 or more cache-hit instructions.
Another example would be a pentium class machine trying
to read or write to an ISA card... icky! Or a pentium class
machine trying to do PIO (progammed I/O), which effectively turns
a pentium pro 200 into a 486 or worse. As long as you
have the cycles to burn, I guess it doesn't matter, but
if you need those cpu cycles, PCI cards and drivers that
support PCI DMA are required.
Microcontrollers also take quick advantage of caching as well.
You can now purchase a $30 single-chip RISC microcontroller
capable of 20+ MIPS using the SAME memory subsystem as an
older non-cached cpu (e.g. 68302) which accesses memory for
every instruction and runs along at a whopping 2 MIPS. Amoung
other things, this makes coprocessors extremely cheap, in
order to allow the main cpu(s) to NOT have to spin expensive
cycles on external accesses.
-Matt