*BSD News Article 7346


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Xref: sserve comp.sys.ibm.pc.hardware:35056 comp.unix.bsd:7395
Newsgroups: comp.sys.ibm.pc.hardware,comp.unix.bsd
Path: sserve!manuel.anu.edu.au!munnari.oz.au!labtam!michael
From: michael@labtam.labtam.oz.au (Michael Podhorodecki)
Subject: Re: ## Info about the Diamond Pixel Clock Synthesizer
Organization: Labtam Australia Pty. Ltd., Melbourne, Australia
Date: Wed, 4 Nov 1992 10:02:08 GMT
Message-ID: <1992Nov4.100208.3900@labtam.labtam.oz.au>
References: <1992Nov02.185531.13576@rz.uni-jena.de>
Lines: 46

>From article <1992Nov02.185531.13576@rz.uni-jena.de>, by pfk@rz.uni-jena.de (Frank Klemm):
> 
> I have found out the programming of the Diamond Pixel Clock Synthesizer. The formula is
> 
> A: Divider 1  [0-7F]
> B: Divider 2  [0-7F]
> C: Divider 3  [0- 3]
> 
> PLL = 14.322 MHz*(A+2)/(B+3)
> 
> |23 22 21 20 19 18 17 16|15 14 13 12 11 10  9  8| 7  6  5  4  3  2  1  0|
>                       +------------------+    +---+ +------------------+
> 			     B			C	     A
> 
> The meaning of the bits 23-17 and 9 are unknown.
> The reprogramming works with 23-17 = [ 0 1 0 0 0 1 0 ] and 9 = [ 0 ] and some
> more combinations.

This matches at least one of the IC Designs Programmable clock generators.
Bits 17 to 20 are then the Index Field which is used to preset the internal
 VCO to an appropiate range. Legal values are typically 0001 to 1101 from low
frequencies to higher, the other values turn clocks off or route them to
different outputs.  Bits 21 to 23 are the register address register field.

> 
> PS: It seem to be that you can also change the 25 MHz and 28 MHz signal. To reset
> these values I must power off the computer. These clocks are not reprogrammed on
> Ctrl Alt Del and RESET !!!!

These parts ihave a power on reset circuit but not a reset pin.
The 25MHz and 28MHz outputs are typical values output by the default
initialised values of the divider registers for the other clock outputs.
These initial values can be masked programmed by the manufacturer.
The registers are programmed by sending manchester encoded serial data,
typically using two for the vga controllers clock lines. You cannot read
the registers back so it is a oneway street especially if you change the
control register.

Has the clock generator IC on the Diamond had its markings removed or what?
If so then I might be able to help identify the part if I have some more
information. However some of the A versions of the IC Designs parts had their
programming algorithims changed and that may explain Diamond's reluctance to
part with programming information.
-- 
Michael Podhorodecki                                michael@labtam.oz.au
Labtam Australia Pty. Ltd.                          Phone: +61-3-587-1444