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From: pfk@rz.uni-jena.de (Frank Klemm)
Newsgroups: comp.sys.ibm.pc.hardware,comp.unix.bsd
Subject: ## Info about the Diamond Pixel Clock Synthesizer
Message-ID: <1992Nov02.185531.13576@rz.uni-jena.de>
Date: 2 Nov 92 18:55:31 GMT
References: <1992Oct24.181837.19994@Informatik.TU-Muenchen.DE> <1992Oct25.034615.5298@netcom.com> <1992Oct25.101257.13662@Informatik.TU-Muenchen.DE> <1992Oct25.222947.6164@netcom.com>,<1992Oct26.105440.21826@Informatik.TU-Muenchen.DE> <1992Oct28.163555.7250@ultb.isc.
Sender: pfk@rz.uni-jena.de (Frank Klemm)
Reply-To: pfk@rz.uni-jena.de (Frank Klemm)
Organization: Friedrich-Schiller-University Jena, Germany
Lines: 40
I have found out the programming of the Diamond Pixel Clock Synthesizer. The formula is
A: Divider 1 [0-7F]
B: Divider 2 [0-7F]
C: Divider 3 [0- 3]
PLL = 14.322 MHz*(A+2)/(B+3)
|23 22 21 20 19 18 17 16|15 14 13 12 11 10 9 8| 7 6 5 4 3 2 1 0|
+------------------+ +---+ +------------------+
B C A
The meaning of the bits 23-17 and 9 are unknown.
The reprogramming works with 23-17 = [ 0 1 0 0 0 1 0 ] and 9 = [ 0 ] and some
more combinations.
If the PLL Frequency is below 25 MHz or above 65 MHz, the PLL generates
a instable ca. 25 MHz or 65 MHz signal, so you can only use the 25-65 MHz
range. This PLL frequency can be divided by 1, 2, 4, or 8 by the divider C.
So the card can generate frequencies from 3 to 65 MHz. How the card generates
a 65 MHz-78 MHz signal (1024x768 70/72 Hz NI) I don't know. BTW: The clock
generator shift register is 24 bit and I found out the meaning of only 16 bit
know. There are 8 bits left.
PS: It seem to be that you can also change the 25 MHz and 28 MHz signal. To reset
these values I must power off the computer. These clocks are not reprogrammed on
Ctrl Alt Del and RESET !!!!
Frank
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| eMail | Frank.Klemm@Physik.Uni-Jena.de || pfk@hpux.rz.uni-jena.de |
| sMail | Frank Klemm, Wiesestr. 27, D-O-6500 Gera, Germany/Europe |
| Tel. | +49 (365) 52712, from Germany: (0365) 52712 |
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