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From: Terry Lambert <terry@lambert.org>
Newsgroups: comp.unix.bsd.freebsd.misc
Subject: Re: Who (or what) is Jesus Monroy?
Date: Fri, 05 Jul 1996 13:30:59 -0700
Organization: Me
Lines: 61
Message-ID: <31DD7B83.5704792A@lambert.org>
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Jesse Monroy wrote:
] : Your claim is that it is useless process data already in L1,
] : L2, and non-collisively accessed memory (assuming a good
] : chipset, or more specifically, a good DMAC), while the I/O
] : bus is active for a DMA transfer.
]
] Well from a practical point, DMA, while
] a good idea, seems to be one of these points
] that CISC processor people like to tout.
] I on the other hand don't see this working
] correctly under parallel processors... as you know.
]
] So now we look at the possbility of
] two or more buses.. and should they be
] parallel or some hybrid of arbitration.
This assumes that the MP system will not use per processor memory
pools with zone allocation, instead of primitive SLAB allocation,
like on Solaris and SVR4 systems (yes, I know the J. Bonwick paper
postdates most other VM publications).
If you want, you can do your SLAB allocation in a page from a
given zone; it's pretty much irrelevant, since the issue of
memory bus arbitration (which seems to be your problem with
DMA) is taken care of with the per processor pools that are
refilled-from/drained-to the global pool at sparse intervals
(Vahalia, "UNIX Internals: The New Frontiers", Chapter 12,
_Kernel Memory Allocation_, 12.9 _A Hierarchical Allocator
for Multiprocessors_ **).
SLAB allocation also tends to fail to perform when its biggest
excuse is taken away (for instance, when the VM and buffer cache
have been unified).
SMP/ASMP is not an argument against DMA. 8-).
] : This is obviously false... you are trolling. The real Jesus
] : Monroy Jr. did not troll.
] :
] : Foo! You are nothing but a charleton!
] :
] So, you can e-mail me... to see if it really is me..
OK, maybe it wasn't as obvious as I thought it was. 8-).
** McKenney, P.E., and Slingwine, J., "Efficient Kernel Memory
Allocation on Shared Memory Multiprocessors," _Proceedings
of Winter 1993 Usenix Technical Conference, Jan 1993, pp.
295-305
Terry Lambert
terry@lambert.org
---
Any opinions in this posting are my own and not those of my present
or previous employers.