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From: migieger@luva.stgt.sub.org (Michael Giegerich)
Subject: Re: FreeBSD: ASUS SP3G and writeback caches
Keywords: FreeBSD
References: <344vevINN2t7j@rs1.rrz.Uni-Koeln.DE> <M47RBQRJ@geminix.in-berlin.de>
Organization: private FreeBSD site
Date: Sun, 4 Sep 1994 17:43:30 GMT
Message-ID: <CvM98w.A22@luva.stgt.sub.org>
Lines: 35
In article <M47RBQRJ@geminix.in-berlin.de>,
Uwe Doering <gemini@geminix.in-berlin.de> wrote:
>se@fileserv1.MI.Uni-Koeln.DE (Stefan Esser) writes:
>
>>Maybe something got broken in going from FreeBSD-1.1 to 1.1.5 ?
>>
>>There have been some reports on problems with the ASUS SP3G
>>and the PCI SCSI driver, if the secondary cache has been
>>configured for writeback operation. The PCI driver makes
>>the NCR do lots of bus master operations to a data area that
>>is written to by the CPU as well (command queues), and is the
>>only FreeBSD driver so far, that depends on cache coherency
>>for PCI to memory operations.
>
>I've seen this problem on an ASUS SP3G with an AHA1542CF controller as
>well (FreeBSD-1.1.5, i486DX2/66 CPU). So I don't think that this is a
>PCI related problem. It's more likely that you need to select `write-
>through' because the current ASUS SP3G doesn't have a Dirty Tag SRAM
>and therefore the secondary cache can't work in `write-back' mode.
>Yes, I know that other MBs work in a pseudo-`write-back' mode even
>without a Dirty Tag SRAM (with reduced performance, of course) but
The SiS Chipset for example supports this pseudo-`write-back'
mode w/o dirty tag ram:
the penality for memory access beyond the L2 cache is hefty:
nearly a doubling of the access time!
So the chipset is better configured as `write-through' in such
cases.
-Michael
--
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Michael Giegerich | migieger@luva.lb.bawue.de
| (migieger@luva.stgt.sub.org)
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