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Path: sserve!newshost.anu.edu.au!harbinger.cc.monash.edu.au!bunyip.cc.uq.oz.au!munnari.oz.au!news.Hawaii.Edu!ames!hookup!yeshua.marcam.com!news.kei.com!MathWorks.Com!solaris.cc.vt.edu!swiss.ans.net!malgudi.oar.net!bronze.coil.com!bronze.coil.com!not-for-mail From: hware@bronze.coil.com (Henry Ware) Newsgroups: comp.os.386bsd.misc Subject: Re: O/S for 286s Date: 8 Aug 1994 23:33:05 -0400 Organization: Central Ohio Internet Link Lines: 38 Message-ID: <326tdh$17u@bronze.coil.com> References: <1994Aug2.170647.1@ualr.edu> <31rn8r$si@s069.infonet.net> <31ugkk$54b@bronze.coil.com> <321f6l$nke@Starbase.NeoSoft.COM> NNTP-Posting-Host: localhost.coil.com In article <321f6l$nke@Starbase.NeoSoft.COM>, Peter da Silva <peter@Starbase.NeoSoft.COM> wrote: >In article <31ugkk$54b@bronze.coil.com>, >Henry Ware <hware@bronze.coil.com> wrote: >>The 286 is really showing its age tho: it can't do virtual memory paging, >>for example. > >I'm not sure that this is true. I do recall noticing that the 286 could >support demand paged virtual memory, though it'd have some weird side >effects. All you need to do demand paging is the ability to recover an >instruction that has caused a memory address trap. The PDP-11 could do >it, though with 8K pages in a 64K address space it wouldn't buy you much. I looked it up- you are right on. The 286 does have some support for vitural memory. When the 286 looks up a segment (in protected mode), it checks to see if the calling process has an appropriate privilege level and it also checks to see if the segment is in memory. It has a maximum logical address space of 1GB/task composed of segments of up to 64kB each. Each segment's size is determined by what it holds, which coupled with the lack of linear addresses make things a little odd, but possible. The 386 explicitly supports paging. Towards this end: it adds 3 new control registers (including a page directory base register and a page fault linear address register); it is able to do a transformation from [logical to] linear to real addresses in hardware (with no time delay); it adds a translation lookaside buffer for storing recently used page table entries (its kinda small: it is two registers); and the logical address space is expanded to 64TB/task, but we normally restrain ourselves to the linear address space of 4GB/task composed of 4kB pages. It would be possible to fix 286 segments at 4k but without hardware support, the gain would be limited. Cheers, Henry -- That does it! I'm putting me back in my kill file!