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Xref: sserve comp.unix.sys5.r3:2002 comp.unix.pc-clone.32bit:6636 biz.sco.general:14879 comp.unix.sys5.r4:7637 comp.unix.unixware:7038 comp.os.linux.misc:18051 comp.os.386bsd.misc:2621 comp.periphs.scsi:21899 comp.sys.ibm.pc.hardware.storage:7063 Path: sserve!newshost.anu.edu.au!harbinger.cc.monash.edu.au!bunyip.cc.uq.oz.au!munnari.oz.au!constellation!news.uoknor.edu!ns1.nodak.edu!netnews.nwnet.net!news.clark.edu!spool.mu.edu!sdd.hp.com!think.com!paperboy.osf.org!usenet From: condict@next19.osf.org (Michael Condict) Newsgroups: comp.unix.sys5.r3,comp.unix.pc-clone.32bit,biz.sco.general,comp.unix.sys5.r4,comp.unix.unixware,comp.os.linux.misc,comp.os.386bsd.misc,comp.periphs.scsi,comp.sys.ibm.pc.hardware.storage Subject: Re: Anyone using a BusLogic 747S with multiple disk drives ? Date: 27 Jun 1994 15:45:32 GMT Organization: Open Software Foundation Lines: 74 Message-ID: <2ums6s$loa@paperboy.osf.org> References: <2u7q64$aj9@saigon.com> NNTP-Posting-Host: next19.osf.org In article <2u7q64$aj9@saigon.com> twc@szebra.Saigon.COM (Ted Chan) writes: > Terry Lambert (terry@cs.weber.edu) wrote: > : In article <2tl4b0$3e0@rand.org> edhall@nntp.rand.org (Ed Hall) writes: > : ] : 5) What kind of system/motherboard are you using > : ] > : ] Nice SuperEISA ver.1 > > : It is (or should be) well known that NiCE EISA motherboards do not > : support bus mastering DMAs in excess of 16M, just like ISA chip sets. > > Ahem, NICE makes at least two lines of EISA boards. One is HiNT based > and the other is SiS based. The latter board does support bus mastering > DMA in excess of 16M. > > As it happens, the SuperEISA Rev 1 board is one of those nice (no pun > intended) SiS EISA chipset based boards that you recommend in your post. > So the problems probably lies elsewhere... > > --twc Double ahem. I have the NICE Mini-EISA motherboard running with an Adaptec 1740 bus-mastering DMA SCSI controller, and *20* MB of memory, without using a bounce buffer. The NICE Mini-EISA motherboard uses the Hint chip-set, but in "Pragmatic EISA" mode, not "Super ISA" mode. The difference between the two is that Pragmatic EISA supports DMA to any 32-bit address. (Neither one supports level-triggered interrupts.) An excerpt about this, from the PC Hardware FAQ (available at rtfm.mit.edu in /pub/usenet/news.answers/pc-hardware-faq), is attached below. -- Michael Condict condict@osf.org OSF Research Inst. (617) 621-7349 1 Cambridge Center Cambridge, MA 02142 -------------------------------------------------------------------------- Q) 2.33 What disadvantages are there to the HiNT EISA chip set? [From: ralf@wpi.wpi.edu (Ralph Valentino)] The HiNT Caesar Chip Set (CS8001 & CS8002) can come in three different configurations. All three of these configurations have EISA style connectors and are (sometimes incorrectly) sold as EISA motherboards. The differences should be carefully noted, though. The rarest of these configuration uses a combination of the first HiNT chip (CS8001) and the Intel chip set. This configuration can support the full EISA functionality: 32 address bits, 32 data bits, level sensitive (sharable) interrupts, full EISA DMA, watch dog (sanity) timer, and so forth. The second configuration is called Super-ISA, which uses both of the HiNT chips. This configuration is very common in low-end models. It supports a very limited functionality: 24 address bits, 32 data bits, edge triggered (non-sharable) interrupts, ISA (16 data, 24 address) DMA, and no watch dog timer. Some EISA boards, such as the Adaptec 1742A EISA Fast SCSI-2 host adapter, can be configured to work in this mode by hacking their EISA configuration file (.CFG) to turn off these features. Other EISA cards require these features and are therefore unusable in these systems. The final configuration is called Pragmatic EISA, or P-EISA. Like Super-ISA, both HiNT chips are used but external support logic (buffers and such) are added to provide a somewhat increased functionality: 32 address bits, 32 data bits, edge triggered (non-sharable) interrupts, ISA (16 data, 24 address) DMA, and no watch dog timer. The full 32 bits for address and data allow bus mastering devices access to the complete range of main memory. As with Super-ISA, there may be incompatibilities with some EISA cards.