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Xref: sserve comp.os.386bsd.development:1730 comp.sys.ibm.pc.hardware.chips:1996 comp.periphs:4959 Newsgroups: comp.os.386bsd.development,comp.sys.ibm.pc.hardware.chips,comp.periphs Path: sserve!newshost.anu.edu.au!munnari.oz.au!bunyip.cc.uq.oz.au!harbinger.cc.monash.edu.au!yeshua.marcam.com!news.kei.com!sol.ctr.columbia.edu!howland.reston.ans.net!agate!apple.com!amd!netcomsv!netcomsv!netcom.com!jmonroy From: jmonroy@netcom.com (Jesus Monroy Jr) Subject: Re: The DMA problem again! Message-ID: <jmonroyCK6Mts.2Ju@netcom.com> Organization: NETCOM On-line Communication Services (408 241-9760 guest) X-Newsreader: TIN [version 1.2 PL1] References: <jmonroyCJxHBH.2x0@netcom.com> <1994Jan22.120513.8484@cc.usu.edu> <jmonroyCK4tFo.3Jx@netcom.com> <CK5AoL.6LL@ucdavis.edu> Date: Tue, 25 Jan 1994 11:05:52 GMT Lines: 21 Greg Shenaut (fzshenau@dale.ucdavis.edu) wrote: : Jesus Monroy Jr (jmonroy@netcom.com) wrote: : [stuff deleted] : : I am saying the inverse (or is it the converse, anyhow). : : I beleive the DMA RAM refresh signal is interfering : : with the FDC transfer. : :: [deleted stuff] :: : Now the _probability_ of this kind of delay occuring as a result of a : refresh cycle is much lower due to the low frequency of refresh cycles, : Wow!!! Somebody too me seriously and gave me a real response. I will study your comments tommorrow in depth and probabley(sp?) include them in the test suite.... -- Jesus Monroy Jr jmonroy@netcom.com Zebra Research /386BSD/device-drivers /fd /qic /clock /documentation ___________________________________________________________________________