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Newsgroups: comp.os.386bsd.development Path: sserve!newshost.anu.edu.au!munnari.oz.au!news.Hawaii.Edu!ames!elroy.jpl.nasa.gov!decwrl!netcomsv!netcom.com!jmonroy From: jmonroy@netcom.com (Jesus Monroy Jr) Subject: Re: [FreeBSD 1.0R] DMA Problems? Message-ID: <jmonroyCJIroC.6AG@netcom.com> Organization: NETCOM On-line Communication Services (408 241-9760 guest) X-Newsreader: TIN [version 1.2 PL1] References: <CHCErs.G5w@genesis.nred.ma.us> <2dj25i$1ga@u.cc.utah.edu> <2encotINN3sq@bonnie.sax.de> <2eqjt7$dqm@u.cc.utah.edu> <CI6291.HBA@genesis.nred.ma.us> <2fbvtoINNk71@bonnie.sax.de> <jmonroyCIJFAr.Atn@netcom.com> <2g4kjvINNnsf@bonnie.sax.de> <jmonroyCJ3ts3.1Ls@netcom.com> <2gk4fjINNal@bonnie.sax.de> <jmonroyCJB69t.D8B@netcom.com> <2gumo6INNi85@bonnie.sax.de> Date: Wed, 12 Jan 1994 13:48:11 GMT Lines: 120 J Wunsch (j@uriah.sax.de) wrote: : jmonroy@netcom.com (Jesus Monroy Jr) writes: : >: You showed the dependance between the timer and the dRAM refresh. But you : >: _assumed_ the timer would control DMA channel 0 without proving this. I : >: claim this is wrong. : >: : > OK. I will say that I have *NOT* proved that DMA : > channel 0 is controlled exclusively by the timer. : Nope. You didn't show that there is really a connection between the timer : and the dma controller. YOU ARE A S S U M I N G THIS! : You proved that modifying the timer causes the dRAM refresh to fail. But : you in no way showed that there is any DMA activity involved. (Or did : you use an oscilloscope?) : OK... I assume that the IBM technical mannual I have in some what relates to my compter... I don't beleive this... Can I clear this up by sending you a copy of the page in the IBM technical reference where "what I assume" is stated? : >: Well i simply wrote a ``4'' onto port ``8'', this should disable the : >: DMA controller. I can prove it does since the floppy fails after this : >: step. But my dRAMs are quite well:-) : >: : > Please clarify this. I don't have my data guide in front : > of me so I can not tell what it is your trying to say. : Bit 2 of the DMA config register 8 controls the overall DMA operation. : Writing a `1' into this bit stops any and all DMA traffic. The failing : floppy shows that the desired effect has been achieved. : OK... in English then, you disabled the controller chip, via the Command REgister (granted it can be call the "config" register). As for what you proved, it is interesting, but it is neither conclusive nor relivant. Someone else pointed this out (so I am not alone on this), the DMA refresh is a psuedo operation. meaning that it does not do a read or a write - - simply a strobe of the address line. What this means is that the "BUS" is active durning this operation, and as a result if the activity of the refresh collides with the FDC transfer we might get a DMAover(under)run. Can I prove this without a shadow of a doubt? NO. I never have stated that I could, I only state that this is the most possible problem/solution. : > OK... what were the results of the "above test"... You : > did not state all the results of your test _nor_ did : > you state if you had run the tests that I had provided. : I've stated all the results of my test. (DMA fails, but RAMs are okay.) : No, what you stated were the conclusions of your test. : Why should i run your test? I could also stop the timer by hand instead : of wasting my time by compiling big programs for this purpose. : Big program? If the main program had more than 100 lines (with comments), I guess this is big? and you got a make file with it also? I think your being stubborn or lazy. : I can : simply stop it with some out's from my debugger. : I don't think your serious. : Well, some seconds later : the system crashes due to the dRAM refresh fail. BUT I CANNOT SHUT UP : THE SAME BOARD BY STOPPING THE DMA ACTIVITIES! Do you now finally believe : that they really, really don't use the DMA chip? : Not on your life.... : > There is some documentation that states that DMA channel 0 : > is available. : DMA channel 0 is not wired to the IO bus, thus it is only available for : mainboard chips (if there are any). : Wait a minute... here in a previous article you stated that some (support) boards can use DMA channel 0!! : >: I hope i gave you enough ``facts and proof'' now. Please don't waste my : >: time anymore. : >: : You gave me two more facts and no proof. If you beleive I'm wasting your time, then don't reply. : [sorry for the offend, shouldn't be] : No offense taken. ~a -- Jesus Monroy Jr jmonroy@netcom.com Zebra Research /386BSD/device-drivers /fd /qic /clock /documentation ___________________________________________________________________________