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From: j@uriah.sax.de (J Wunsch)
Newsgroups: comp.os.386bsd.development
Subject: Re: [FreeBSD 1.0R] DMA Problems?
Date: 11 Jan 1994 18:13:42 +0100
Organization: Private U**X site; member IN e.V.
Lines: 54
Message-ID: <2gumo6INNi85@bonnie.sax.de>
References: <CHCErs.G5w@genesis.nred.ma.us> <2dj25i$1ga@u.cc.utah.edu> <2encotINN3sq@bonnie.sax.de> <2eqjt7$dqm@u.cc.utah.edu> <CI6291.HBA@genesis.nred.ma.us> <2fbvtoINNk71@bonnie.sax.de> <jmonroyCIJFAr.Atn@netcom.com> <2g4kjvINNnsf@bonnie.sax.de> <jmonroyCJ3ts3.1Ls@netcom.com> <2gk4fjINNal@bonnie.sax.de> <jmonroyCJB69t.D8B@netcom.com>
NNTP-Posting-Host: bonnie.sax.de
jmonroy@netcom.com (Jesus Monroy Jr) writes:
>: You showed the dependance between the timer and the dRAM refresh. But you
>: _assumed_ the timer would control DMA channel 0 without proving this. I
>: claim this is wrong.
>:
> OK. I will say that I have *NOT* proved that DMA
> channel 0 is controlled exclusively by the timer.
Nope. You didn't show that there is really a connection between the timer
and the dma controller. YOU ARE A S S U M I N G THIS!
You proved that modifying the timer causes the dRAM refresh to fail. But
you in no way showed that there is any DMA activity involved. (Or did
you use an oscilloscope?)
>: Well i simply wrote a ``4'' onto port ``8'', this should disable the
>: DMA controller. I can prove it does since the floppy fails after this
>: step. But my dRAMs are quite well:-)
>:
> Please clarify this. I don't have my data guide in front
> of me so I can not tell what it is your trying to say.
Bit 2 of the DMA config register 8 controls the overall DMA operation.
Writing a `1' into this bit stops any and all DMA traffic. The failing
floppy shows that the desired effect has been achieved.
> OK... what were the results of the "above test"... You
> did not state all the results of your test _nor_ did
> you state if you had run the tests that I had provided.
I've stated all the results of my test. (DMA fails, but RAMs are okay.)
Why should i run your test? I could also stop the timer by hand instead
of wasting my time by compiling big programs for this purpose. I can
simply stop it with some out's from my debugger. Well, some seconds later
the system crashes due to the dRAM refresh fail. BUT I CANNOT SHUT UP
THE SAME BOARD BY STOPPING THE DMA ACTIVITIES! Do you now finally believe
that they really, really don't use the DMA chip?
> There is some documentation that states that DMA channel 0
> is available.
DMA channel 0 is not wired to the IO bus, thus it is only available for
mainboard chips (if there are any).
>: I hope i gave you enough ``facts and proof'' now. Please don't waste my
>: time anymore.
>:
[sorry for the offend, shouldn't be]
--
in real life: J"org Wunsch | ) o o | primary: joerg_wunsch@tcd-dresden.de
above 1.8 MHz: DL 8 DTL | ) | | private: joerg_wunsch@uriah.sax.de
| . * ) == |
``An elephant is a mouse with an operating system.''