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Path: sserve!newshost.anu.edu.au!munnari.oz.au!news.Hawaii.Edu!ames!agate!soda.berkeley.edu!wjolitz From: wjolitz@soda.berkeley.edu (William F. Jolitz) Newsgroups: comp.os.386bsd.development Subject: Re: baffled by inbs in INTR(..) Date: 9 Jun 1993 21:09:19 GMT Organization: U.C. Berkeley, CS Undergraduate Association Lines: 29 Message-ID: <1v5jhv$15d@agate.berkeley.edu> References: <C8DC66.9My@world.std.com> NNTP-Posting-Host: soda.berkeley.edu In article <C8DC66.9My@world.std.com> hd@world.std.com (HD Associates) writes: >I was looking at the preamble for the ISRs in i386/isa/icu.h >the other day and was baffled by the inbs: > [code fragment] >It appears that each access to the PIC is bracketed by an inb to the >mystery (to me) port 0x84. Yes, this is correct. >What is this, and what is the logic? Is this a well known hack? Is >this the I/O world's version of a NOP? The point of this is to defeat the "write posting" of some chipsets. What happens is that the last writes to memory and the last I/O output instruction is sometimes buffered inside the chipset until the next input instruction. This is the case with 486 and some EISA systems. If this isn't present, then the masks don't get updated by the time that the sti instruction executes, so the interrupt will occur until you overflow the kernel stack and the machine resets. The selection of port 84 is that this is a port known to be unselected. Thus, nothing will be gated onto the bus. Documentation for this resides in the Compaq Technical Reference Guide for SystemPros. Bill Jolitz.